To improve the testability of high density semiconductor devices, modern design practice inserts additional circuitry specific to test, such as scan chains. Defects in scan chains are becoming more common as technology nodes decrease in size and the number of flip-flops in a design increase. Problems often surface in scan chains as mission-critical interconnects are routed first, and scan interconnects are routed later to avoid interfering with the mission-critical layout of the device. A scan chain in test mode is configured to be a very long shift register. If a scan chain is blocked, the tester loses observability and controllability within the circuit and records a massive amount of failures.
As technology nodes shrink, more defects are found in the scan chain circuitry added for the purpose of test. This is due to a number of reasons as described in this document. To bring new integrated circuits to market, and ramp yield to acceptable levels, identifying these defects and learning trends is critical, but can be costly without new approaches.
Scan Basics
To explain the new software process, it is first necessary to provide some background on established techniques of SCAN in semiconductor test. The approach of scan methodology is to replace all flip-flops 102, 104, 106, 108 (FIG. 1) in a design 100 with scan flip-flops 200, 202, 204, 206 (FIG. 2). Scan flip-flops provide two paths into each flip-flop: one (e.g., 208) for the mission of the design, and a second (e.g., 210) to facilitate test.
Scan Flip-Flops
There are two most common methods of implementation today:
MUXD—This scan flip-flop approach places a multiplexer commonly referred to as a mux on the front end of the D-input. The selector to the mux, known as the scan enable, determines whether to use the mission mode input or the scan test input.
LSSD—Another common scan flip-flop approach is to use two clocks. One clock latches the mission path input into the flip-flop while the second clock latches the scan test input data into the flip-flop.
Scan Chains
By stitching all of the scan flip-flops 200, 202, 204, 206 (FIG. 2), or scan cells, together into one or more scan chains 212, each flip-flop can be preset or observed. This allows for test patterns to be constructed which will concentrate on finding faults in mini sub-circuits. See the following circuit example. The first illustration FIG. 1 shows the circuit 100 prior to scan insertion, and the second FIG. 2 shows the circuit 100 after a MUXD scan insertion.
In FIG. 2, notice that each flip-flop (e.g., 202) has two input paths (e.g., 208, 210) as controlled by a mux (e.g., 214) on the input. When the scan enable “SE” 216 is asserted, the scan chain 212 operates as a shift register. This allows for each flip-flop 200, 202, 204, 206 to be set to a specific state. It also allows for the observation of each flip-flop state as the values are shifted out of the device onto the scan output “SO”218. We have numbered each flip-flop, or scan cell, for the purpose of referencing (i.e., numbers “0”-“3”in FIG. 2).
For this example, the ‘and’ gate 220 can be tested by shifting data into scan cells 3 and 2. After the desired test condition has been loaded, the scan enable is de-asserted and a clock 222 can be applied to capture the output of the combinational logic as observed at scan cell 1. The scan enable is once more applied and the result data as captured at scan cell 1 can be shifted through the scan chain until it can be seen on the device output for the scan chain.
Defect Models for Scan Chains
Defects in scan chains are becoming increasingly common as technology nodes decrease in size and the number of flip-flops in newer designs grow. Problems often result in scan chains due to the priority of routing in which mission critical interconnects are routed first, and scan interconnects are routed later to avoid interfering with the mission critical layout of the device.
There are a few generally used models for defects in scan chains: blocked chain defect, bridging defect, and hold-time defect.
Blocked Chains
The effect of a blocked chain defect can be determined by observing the scan outputs while in scan mode. If the output of a chain is at a fixed level regardless of the data shifted into the chain, the chain is blocked at one or more points.
Bridging
The effect of a bridging defect can often be determined by observing the number of output changes in chain tests as compared to the number of input changes. As scan chains are essentially very long shift registers when in test mode, what goes in should come out. Regardless of whether the output matches the input, if the output is consistent per the pattern applied, changing one bit on the input pattern should result in a one bit change on the output. If two or more bits change, this is an indication of a bridging condition.
Hold-Time
Due to excessively long wire routes as compared to Clock to Q times of flip-flops, there may not be ample hold-time on the input of one scan flip-flop prior to the change of data on the Q-output of the previous flip-flop in the chain. This condition can be determined by streaming a small number of bits of one data state surrounded by a background of the inverse data state. If the number of bits applied into the chain is decreased as the data exits the scan output, it is likely that a hold-time problem exists.
Testing the Scan Chains
Typically, to insure that the scan chain test logic is operational, tests will be performed on it prior to the functional logic. The most common approach is to present a series of I's and 0's at the Scan Inputs (SI) 224 (FIG. 3). With the Scan Enable (SE) 216 asserted, the scan chain 212 is essentially a long shift register. Again, with the assertion of the Scan Enable (SE) 216, the functional logic is removed from the test. After ‘n’ number of clock cycles, where ‘n’ equals the number of scan cells in the chain, the input stream should be observed on the Scan Output (SO) 218. See the example in FIG. 3.
The Problem: The Blocked Scan Chain
If the scan chain is blocked, the output data will be a solid stream of either 1's or 0's after enough clock cycles are applied to flush the scan cells after the break position. This blockage 400 (FIG. 4), which is becomes more common in smaller nanometer geometries, can be caused either by manufacturing defects, or design errors.
Conventional chain test patterns are implemented as a replicated stream of a ‘0-0-1-1’ sequence, with the result as seen by testers today being a pass/fail result signature of ‘pass-pass-fail-fail’ or ‘fail-fail-pass-pass’. By recognizing this signature, it could be determined that the chain is broken. However, nothing is known about where inside the chain the break 400 exists. See FIG. 4.
It should be pointed out that while the scan output will be a solid stream of either 1's or 0's after a number of clocks are applied equal to the number of scan cells between the output and the block point, the output may, and most all cases will, reach that static output level much prior to the number of clocks.
Functional Tester Background
Historically, testers apply a set of simulated stimulus, and validate that the response on the device outputs match the results expected from the simulation. Functional testers are designed to report in a go/no-go fashion that all of the outputs matched the expected results for all checked strobe points or not. Functional testers are not architected to understand design criteria of the device under test such as the scan structures. Thus, while testers can understand which output signals contained failures, each output signal can represent tens of thousands of internal scan cells.
Thus it can be appreciated that what is needed is a real-time analysis capability, to detect and locate a break in a scan chain while the device under test is still mounted on the automated test equipment, which does not require a special test vector set, which can be applied to any generally useful commercially provided test patterns, which eliminates the need for extensive offline storage, computation, or analysis, and which reduces the amount of data logged to obtain meaningful results to a manageable volume.